We received a guest from Barcelona, Miquel Moretó, this week at Polytechnique! Miquel holds a dual degree in Mathematics and Telecommunication Engineering, and is an associate professor in Computer Architectures at UPC (Spain), as well as one of the leading researchers of the Barcelona Supercomputing Center (BSC), Spain’s national supercomputer. On Wednesday, he presented the BSC and the main research and development projects and industrial collaborations that are carried on the supercomputer premises.
BSC hosts MareNostrum 5, one of the main supercomputers part of the European High Performance Computing Joint Undertaking (EuroHPC), and is particularly involved in RISC-V European chip design efforts, which includes the European Processor Initiative (EPI), the Lagarto/Sargantana chip, fully designed at BSC and for which the 3rd generation was presented in December 2023, and other projects supported by the European Chips Act, NextGenerationEU funds, and related national initiatives. Miquel is leading BSC’s research efforts on design and development of RISC-V architectures, in particular the Lagarto initiative; and shared with us his impressions on the RISC-V revolution, which opens new and exciting perspectives for chip design and development, e.g. specialized CPUs or System-on-Chips (SoC) for supercomputers, datacenters and servers. (The slides of his presentation can be found here.)
The short visit, presentation and insights of Miquel on RISC-V, chip design and High Performance Computing led to a lively round of questions and exchanges with researchers and students from Polytechnique — which allows us to hope for fruitful collaborations and exchanges to come between UPC, BSC, and the institutions at the Institut Polytechnique de Paris. “The beginning (continuation, in this case) of a beautiful friendship”, to put it in terms of Casablanca ;).